Frost
Autogen
Overview
Developing complete HDL projects is a complicated and lengthy task that can be a barrier to developing algorithms for an FPGA. While the HDL can be synthesized with tools such as Mathworks’ HDL coder, it must still be connected to the system, which likely involves wrapping them in another component with the desired interfaces. The autogeneration software is a code generation tool designed to simplify this process and make development more accessible. The autogeneration software leverages Mathworks’ HDL coder to generate custom VHDL components from a Simulink model, then automatically creates wrappers for these components, and generates and compiles fully functional Quartus projects. Furthermore, the autogeneration tool also creates Linux loadable kernel modules that can be used to access tunable parameters in the VHDL components as well as interface files that can be used by the FPGA Open Speech Tools web application to easily modify these registers.
Development Process
The process begins with a Simulink model and a set of associated Matlab scripts, known here as "Simulink model init scripts". The init scripts contain information about model parameters (clock rates, registers ,etc.) and setup/takedown for simulation stimuli.
Information from the model and init scripts are used to create an intermediate dataplane configuration file that most of the downstream utilities use.This dataplane configuration file is the interface between MATLAB and external scripts; separating the code generation from Matlab keeps everything modular, as well as enabling the code generation to be used without MATLAB/Simulink.
MATLAB's HDL Coder takes care of most of the HDL coder generation. A python script generates an Avalon wrapper for the MATLAB-generated HDL so it is compatible with the Avalon interfaces we use in our Quartus projects. Another python script generates a TCL file that creates a Platform Designer IP core with the generated HDL files. The TCL file and HDL files make up what we call the Simulink algorithm's "IP Core".
Using information in the dataplane configuration file, some Python scripts create C code for a Linux device driver that will control registers in the IP core. Another Python script generates a Makefile and a Kbuild file based upon the Simulink model's (and, by extension, the C code's) name; these files are used to compile the device driver into a loadable kernel module.
A set of python functions creates/copies files needed for a Quartus project. The Simulink algorithm IP core is added to a Platform Designer system automatically between the input and output of the AD1939 audio codec component. These Python functions also compile the Quartus project. After a successful compilation, Quartus calls TCL scripts that convert the FPGA bitstream to an rbf (raw binary file). It is planned that Quartus will call TCL scripts to generate a device tree overlay for the project/algorithm as well.
To enable autogenerating a GUI, two configuration files are created: a UI configuration and a Linker configuration. The information needed to create these files is stored in structs that define the registers in the model. The UI configuration is used by the autogen webapp to create a UI to control registers. The Linker configuration is used to map the UI controls to the registers' filepaths in Linux's sysfs pseudo filesystem.